Field effect transistors are widely used in microelectronic devices including, but not limited to, microprocessors and memory devices. Field effect transistors are also widely used as power semiconductor devices, i.e. devices which are capable of handling high currents and voltages.
One example of a field effect transistor which is used as a power device is a driver integrated circuit (IC) which drives a liquid crystal display. It is generally desirable for a driver IC to have a high breakdown voltage, high operating voltage, high driver current and low on-state resistance. In order to satisfy these conditions, a driver IC is generally designed to have a high resistance diffused layer which is doped at a low density. However, as the density of the diffused layer is lowered, the breakdown voltage may increase and the current driving capability may be lowered. Also, the on-state resistance may increase. In order to overcome these problems, it is known to provide a driver integrated circuit having a large channel width and a large driver chip size.
In order to overcome these and other problems, it has also been proposed to use double diffused metal oxide semiconductor (DMOS) transistors, and/or MOS Field Effect Transistors (MOSFETs) having a lightly doped drain (LDD) or a double diffused drain (DDD). However, these structures may also have drawbacks. For example, the DMOS transistor may have a high operating voltage, but may occupy a large area in a microelectronic substrate. As another example, for field effect transistors having DDD or LDD structures, it may be difficult to obtain a sufficiently high operating voltage.
In order to reduce the on-state resistance of a field effect transistor, it is known to increase the current flow between the source and drain thereof, while increasing the channel width. See, for example, U.S. Pat. No. 4,393,391 entitled "Power MOS Transistor With a Plurality of Longitudinal Grooves to Increase Channel Conducting Area", which discloses a technique for increasing the channel width by forming grooves on a surface of a substrate and forming a gate thereon.
FIGS. 1 and 2 illustrate a field effect transistor according to U.S. Pat. No. 4,393,391. FIG. 1 is a perspective view of this transistor, and FIG. 2 is a cross-sectional view taken along the lines II-II' of FIG. 1.
As shown in FIGS. 1 and 2, ridges 4A and furrows 4B are formed in a semiconductor substrate 1 by forming grooves or trenches in a face of the substrate 1. A source 2 and a drain 3 are formed on respective ends of the ridges 4A and the furrows 4B. A gate oxide layer 5 and a gate electrode 7 are then formed on the surfaces of the ridges 4A and the furrows 4B. As illustrated in FIG. 1, the width W of the channel can be increased by the ridge and furrow portions, while the length of the channel may be maintained as is, so that the on-state resistance can be reduced.
Unfortunately, although this technique is directly applicable to field effect transistors having identical widths at the source end and the drain end of the channel, it may not be suitable for field effect transistors where the channel width at the source end and drain end of the channel are substantially different from one another. For example, if the source is formed inside a ring-shaped (also referred to as doughnut-shaped) gate electrode and the drain is formed outside the gate electrode, the decrease of the on-state resistance and the increase of the driver current may only be obtained in proportion to the increase of the width of the source end of the channel. However, increases in the width in the source end of the channel may be limited by the field effect transistor design. This in turn may limit the increase in the width at the drain end of the channel.